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Source code

Details

Name: axi_slave
Created: Apr 5, 2011
Updated: Apr 19, 2011
SVN Updated: Jul 3, 2011

Other project properties

Category: Testing / Verification
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address bits, data bits, AXI command depth, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools