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Source code

Details

Name: axi_master
Created: Apr 3, 2011
Updated: Oct 21, 2013
SVN Updated: Jul 3, 2011

Other project properties

Category: Testing / Verification
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

Generic AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: ID number, data bits, AXI command depth, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools