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Name: zorro_to_wishbone_bridge
Created: Jun 23, 2010
Updated: Mar 9, 2012
SVN Updated: Jan 11, 2012

Other project properties

Category: System on Chip
Language: Verilog
Development status: Planning
Additional info:
WishBone Compliant: Yes
License: LGPL


This project is in the early planning stage. I am collecting documentation for both busses and beginning to understand them, and refining the specifications. I'm collecting tools for design and test and preparing a development environment on my computer. I'm currently taking a VHDL course at university, and thus will plan to have both Verilog and VHDL versions of this bridge. Progress on this design will hopefully pick up this summer 2012.
I intend to use as many freely available tools as possible, and will have some learning curve to be productive with them. I'm fairly familiar with simulating in Simvision, but I'd like to be doing this project with Icarus Verilog and GTKWave or Dinotrace instead, which I have never used before... I'm also interested in Verilator, but sounds like I'd need to learn SystemC for testbench stuff in that, and I'd also like to see things run in gplcver.
I've decided to make the RTL and any Makefiles, scripts, etc. in this project to be LGPL 2.1 or later. I'd pondered making documentation for this project under GFDL, but after discussions in various forums, I'm now planning for documentation (specs, test plans, etc) to be under LGPL 2.1 or later as well. While I'm told I can separate the two portions of this project into different licenses, it could forbid deriving any documentation from RTL etc. While I don't at the moment plan to derive docs from RTL or Makefiles, I might as well make it easy to do that if I change my mind, so the whole shebang will now be LGPL 2.1 or later.
I've started working on a specification document in OpenOffice. I'm hoping to do a decent document before I get lost in RTL coding and find myself hacking around more than should be, even as I don't expect this to be a hugely complex project. Surprusingly I've had a couple people ask about this project, unfortunately I'm still trying to find time to work on a spec. I've not yet written any RTL, I'd really like to do a spec first, and that will apparently take a while to get through. I'd love to have this done and up, but for now there's not yet anything worth looking at. I am getting a little better understanding of Wishbone's burst cycle styles and the PCB adapters I need for my FPGA on a PCI card to test in an Amiga Zorro slot.
Surprisingly the 124 pins PCI bus (yes I knew there are key "pins" that maybe shouldn't count) does not have enough signal pins to make up a 100pin Zorro slot. I believe the 25x2 header on my FPGA board should be able to complement the PCI edge to fill in the missing places. Unfortunately those pins are shared with the AvBus P4 connector, which may or may not conflict with the memory and communications modules I'd like to put there. Regardless I'll need to add quickswitches as it looks like the 25x2 is unbuffered to the FPGA pins. I'll probably put some additional things on the 25x2 part of the Zorro adapter for IDE, SCSI, maybe a couple other things to maximize what I can possibly use there.

Source Code

To check out the SVN trunk for this project:
[code]svn co http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge/trunk [/code]
In Eclipse, using Subversive Plugin:
URL = http://opencores.org/ocsvn/zorro_to_wishbone_bridge/zorro_to_wishbone_bridge
fill in your opencores.org login info
choose trunk or whatever to check out to your new project.


This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus. I suppose this will really end up being two bridges, one for each direction.
I am learning Verilog RTL for SoC/ASIC design and testbench simulation at work, and I think this will be an interesting "other than my day job" project to gain more experience with Verilog coding, tools, FPGA boards and FPGA tools. I also think that the Amiga in an FPGA community will benefit from gaining access to the numerous Wishbone peripheral cores here at opencores.org.
This project will be based on Zorro bus documentation as found in

  1. the Commodore Amiga A3000T Service Manual
  2. the Commodore-Amiga Inc. Zorro III Bus Specification rev 1.10
  3. the Commodore Amiga A500/A2000 Technical Reference Manual
  4. the Commodore-Amiga Inc. Amiga Hardware Reference Manual 3rd Edition
  5. and other service manuals that seem relevant in my collection.

This project will bridge to/from Wishbone Rev.B4, taking advantage of as many B4 features as makes sense for the old ZorroII/ZorroIII protocols.
For those interested in using this to fit a Wishbone peripheral into a Zorro host, you will need to obtain an Autoconfig Manufacturer ID if you do not already have one. (Please, please, do not hijack IDs belonging to someone else. Lets do this right, even if so many are no longer active) Contact Olaf Barthel to obtain an official Manufacturer ID. (I need to ask how he would prefer to be contacted for this, but he can be found on utilitybase now and then when the site is working, but use NoScript or something like it is recommended to avoid the site vandals). For those interested in connecting Zorro peripherals to a Wishbone host, you will not need an Autoconfig ID set, as the bridge intends to be a transparent interface to the Zorro bus protocols, not to be a "known peripheral" itself.
Why not just have an Autoconfig ID set for the bridge itself? Well, what the OS drivers really need to know is what peripherals are out there, not how they are connected. One designer might use this bridge to connect a Wishbone IDE controller. Another may connect a Wishbone Ethernet MAC. Another may connect a Wishbone DDR memory controller. And another may connect a combination of things. Your ID set tells the system what all peripherals are on your board, via some level of the hardware device tree. Knowing which board this is lets the firmware/OS determine what peripherals are there, where they are in address space, and then it can connect appropriate chip/device drivers. I would hope that any such products will use a board/chip style driver system as demonstrated by Picasso96 graphics card API. This would allow a single driver to be used for common peripharal IPs, regardless of who's board they are on, or what other things are configured with it on the other side of each particular bridge. I don't know the general Amiga expansion API well enough to say if this is already the case or no tin general, or just in certain cases. It may or may not be the way things are already for your particular driver needs.
There are three possible uses for this bridge:
  • as a Zorro slave peripheral card plugged into an Amiga motherboard Zorro slot
  • as a Zorro bus master peripheral card plugged into an Amiga motherboard Zorro slot
  • as a Zorro system controller on some motherboard which is in control of that motherboard's various Zorro slots (ie. it watches all busmaster acknowledge signals from all slots, sends busmaster grant signals to all slots, determines which acknowledge to send and when, etc. which are beyond a peripheral busmaster card's responsibilities) This is the mode which will be interesting to people wanting to add Zorro slots to the open-sourced MiniMig Amiga in an FPGA project as one example, as the system needs more control capabilities than a busmaster peripheral does. This is also the mode of interest if anyone wishes to create a replacement for Commodore's SuperBuster system bus controller chip.

I plan to implement this bridge in three main phases, following the three usage modes as they seem to go in a nice order of complexity and build on previous modes:
Phase 1: Implement Zorro II / Zorro III slave peripheral mode to Wishbone master bus. This allows connecting a Wishbone slave peripheral to a Zorro host system. (Zorro slaves may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus)
  • Phase 1a will be ZorroII host/master to Wishbone peripheral/slave
  • Phase 1b will be ZorroIII host/master to Wishbone peripheral/slave
Phase 2: Implement Zorro II / Zorro III busmaster peripheral mode to Wishbone slave bus. This allows connecting a Wishbone master bus/peripheral to a Zorro slave. This should allow two uses:
  • Wishbone master peripheral on a Zorro busmastering peripheral plugin card, inserted into a Zorro host system.
    • Phase 2a ZorroII host to Wishbone master peripheral
    • Phase 2b ZorroIII host to Wishbone master peripheral
  • Wishbone host system can use one, possibly multiple Zorro slave peripheral plugin cards, but no Zorro busmastering peripheral plugin cards. (busmaster capable Zorro cards should work fine as slaves, and may be able to DMA into the host system under direction from the host system driver software, but will not be able to request control of the bus due to lack of Zorro bus arbitration logic)
    • Phase 2c Wishbone host to ZorroII master peripheral
    • Phase 2d Wishbone host to ZorroIII master peripheral
Phase 3: Implement Zorro II / Zorro III system bus controller mode, which adds in Zorro bus arbitration logic. This will allow a Wishbone host system full use of all Zorro slave and busmaster peripheral plugin cards to request control of the bus and DMA into the host system. It's possible that this may be little more than pairing Phase 2 with an existing OpenCores or other suitable arbiter. I think it should be desirable to reuse as much existing IP as possible. (with compatible licensing of course)

Testing of this core will utilize an Avnet Xilinx® Spartan®-3 Evaluation Kit, which is a PCI card format eval/development system including a Xilinx Spartan 3 XC3S1500 FPGA device.
  1. A small adapter board will allow the 100pin Zorro edge connector to fit onto this FPGA board's PCI edge connector when testing slave and busmaster peripheral modes in an Amiga 3000 desktop and/or A4000T computer. Host Amiga computer will use a SuperBuster rev 11 system bus controller chip to control its Zorro bus. I need to verify that the PCI edgecard on my Spartan3 board can be treated this way, or if the onboard levelshifting groups prohibit direct Zorro slot compatibility.
  2. Another adapter board will be made to provide a connection to an Amiga 4000 desktop computer's Zorro backplane daughterboard, possibly also the Amiga 3000 desktop computer's equivalent if supporting both is reasonable. This easily provides for a number of Zorro slots while reducing PCB board design on my part. Testing in this mode will likely include aoOCS and porting the MiniMig , DragonBall/68K Wishbone interface , and ao68000 or ae68 cores to my evaluation board. This combination should give me a Wishbone Minimig core attached to a Wishbone CPU, everything in verilog, where the traditionally Minimig-paired TG68 is a VHDL non-Wishbone CPU. A single HDL language should make life easier on me, as will existing Wishbone CPU and interface to Minimig's 68000 bus. Again I need to verify that the level shifting groupings on the Spartan3 board allow direct Zorro bus connection.
  3. Any adapter PCBs will be open-sourced as part of this project, and will be in Eagle schematic/board file format.