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Source code

Details

Name: wisbone_2_ahb
Created: Aug 6, 2007
Updated: Feb 17, 2015
SVN Updated: Mar 10, 2009

Other project properties

Category: System on Chip
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License:

WISHBONE Protocol to AHB Protocol Bridge.

Features

- AHB 2.0 compliant
- Wishbone B.3 compliant
- WISHBONE Burst NOT SUPPORTED
- Fully synthesisable
- Synchronous
- Verilog RTL
- Includes a Verilog Testbench with 9 Testcases

Status

- RTL : Complete
- Testbench : Complete
- Document : Complete