Go Back

Source code

Details

Name: wishbone_out_port
Created: Jan 27, 2008
Updated: Jan 29, 2008
SVN Updated: Mar 10, 2009

Other project properties

Category: System on Chip
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: Yes
License: LGPL

Description

Are you using Wishbone, do you need some simple 'slaves' to test your bus with ?
Well, the Wishbone spec, appendix B3, has VHDL examples of Wishbone outports, and memories.
This is the code from B3 ! saves one copying the PDF each time.

Features

- Can be simulated and can be synthesised.

Status

Simulated in XST 9.2 sp 4
Synthesised to Spartan FPGA.