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Source code

Details

Name: wb_conmax
Created: Oct 23, 2001
Updated: Feb 10, 2004
SVN Updated: Mar 10, 2009

Other project properties

Category: System on Chip
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: Yes
License:

Description

This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves
Some of the main features are:
- Up to 8 Masters
- Up to 16 Slaves
- 1, 2 or 4 priority levels
- Fully configurable

IMAGE: conmax.jpg

FILE: conmax.jpg DESCRIPTION: Example SoC with the CONMAX IP Core

Status

- October 2002, Maintenance update: Fixed a typo in parameter passing and in the specification
- May 2002. Several users of the core have reported that the core performs as specified. Project is now considered completed.
- 10/19/2001 Initial Release.
- I will post a message to cores@opencores.org each time I have an update

Change log

- 10/19/2001 Initial Reslease


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This IP Core is provided by:

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