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Source code


Name: wb_builder
Created: Apr 26, 2004
Updated: Oct 3, 2014
SVN Updated: Mar 20, 2013

Other project properties

Category: System on Chip
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: Yes

To do

- add verilog output

Known errors

- when data bus size is 8 bits the script generates wishbone sel signals which are of no use


- GUI for easy startup
- supports both shared bus and csorrbarswitch topology


- design tested in HDL simulator and in FPGA (ALTERA C12)
- current design only support VHDL output


The intention is to provide an easy way to create and change a system based on the WISHBONE bus. The user shall be able to try different configurations to achieve an area/performance optimized design.
WISHBONE builder is a script which generates a wishbone interconnect matrix in HDL. The user defines the functionallity of the wishbone bus in a text file or via a GUI. The tools then generates the HDL implementation.
The core supports both shared bus and crossbar switch implementations.
To run the WISHBONE builder you must have installed PERL. A windows executable can be found at http://www.activestate.com/. In Linux PERL is usually installed with the system. The GUI uses a PERL module called Tk. Tk can be found at CPAN, http://www.cpan.org/.