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Source code


Name: sardmips
Created: Jan 21, 2006
Updated: Feb 9, 2006
SVN Updated: Mar 10, 2009

Other project properties

Category: System on Chip
Language: Other
Development status: Alpha
Additional info:
WishBone Compliant: No
License: GPL

Embedded MIPS R2000

It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable.


- feature1
- feature1.1


Some bugs was fix.
-> correct bug when intterupt occur during MFLO and MFHI instruction.
Now I'm working on the CP0
status 2