Created: Sep 25, 2011
Updated: Sep 25, 2011
SVN Updated: Sep 30, 2011
Other project properties
System on Chip
Language: Verilog & VHDL
Development status: Alpha
WishBone Compliant: Yes
This is a complete system-on-a-chip.
Developed on a Diligent Spartan3e board, the SOC includes CPU (TG68), bitmap and text displays, PSG, keyboard and more.
52x31 text display
416 x 262 bitmapped graphics display
line draw accelerator
4 channel ADSR PSG (not working at the moment)
random number generator
PS2 compatible keyboard interface
RS232 interface UART
The SOC make use of the TG68 cpu core available at OpenCores.org. This fine core implements the MC68000 instruction set.
The Nexys Epp memory controller available on the Diligent site is used for external communications to the PSRAM and Flash ROM.
Also used are the rtfTextController and rtfBitmap Controller cores found elsewhere on OpenCores.org.
The chip a Spartan 3eS1200e is full!
WISHBONE bus is used for core interconnects.
There are about a half dozen devices that can act as bus masters for the onboard PSRAM. These are all connected through a memory controller. Devices have a fixed priority arrangement for access to the RAM with burst bitmap video having the highest priority. During developement a 2k RAM and BIOS rom were connected on a private cpu bus to make it easier to get the cpu going.
A PS2 compatible keyboard interface recieves scan codes from the keyboard which is then converted to ascii using a scan-code lookup table in hardware. Ctrl-Alt-Del is wired to the processor's NMI signal to allow the system to be reset.
A WXGA video sync generator supplies timing to several video cores. The video cores are connected together to form a video pipeline. The switches on the FPGA board may be used to switch on and off several video devices.
A modified version Gordo's Tiny Basic 1.2 is used and occupies the last part of the BIOS ROM. The Poke and peek commands can be used to control the devices in the system. Currently added to the tiny basic are a couple of graphics commands: LINE x0,y0,x1,y1. POINT x,y. AND PENCOLOR c. There is also a small ROM monitor. The ROM monitor allows dumping memory, and jumping to code.