Created: Aug 6, 2014
Updated: Sep 28, 2014
SVN Updated: Sep 28, 2014
Other project properties
System on Chip
Development status: Mature
WishBone Compliant: No
The project is RT level design of image component labeling and feature extraction. The design is captured in VHDL. The architecture is parallel and pipelined.
The project is posted under LPGL license. User need to give reference to the publishes work when used in design.
Hardware Architecture for Real-time Component Feature Descriptors on a FPGA
Abdul Waheed Malik, Benny Thörnberg, Najeem Lawal, Muhammad Imran
publication in Internal Journal of Distributed Sensors, special issue on
“Recent advances in Wireless Visual Sensor Network (WVSN)”
Comparison of Three Smart Camera Architectures for Real-Time Machine Vision
Abdul Waheed Malik, Benny Thörnberg and Prasanna Kumar
publication in International Journal of Advanced Robotic Systems