Created: Jan 13, 2014
Updated: Apr 19, 2014
SVN Updated: Mar 19, 2014
Other project properties
System on Chip
Development status: Mature
Additional info: FPGA proven
WishBone Compliant: Yes
This project aims to present an open-source, platform independent MPSoC, targeting FPGA implementation.
The NoC based MPSoC is generated by connecting the processing tiles via a low latency NoC network. A processing tile includes one aeMB processor, RAM, NoC interface adapter, and other optional peripheral devices such as GPIO, timer, external interrupts and interrupt controller. All components inside a tile are connected using wishbone bus. The processing tiles can have different number of peripheral devices, which is defined using parameter.
In this project A two clock-cycles pipelined wormhole virtual channel network-on-chip (NoC) router RTL is proposed. The router first pipeline stage is the parallel look-ahead route computation with a non-speculative VC/switch allocation. The second stage is the crossbar switch traversal. The proposed router micro-architecture is optimized in three main criteria of hardware cost, maximum operating frequency and QoS compared to existing related works.
Two Network interface (NI) modules are proposed: one for connecting the processor core to NoC via wishbone bus. The proposed NI is able to read and write on the processor data memory in a DMA fashion. Another NI is designed to connect any shared memory (eg. external SDRAM) to NoC.
We tested our NoC based MPSoC on DE2-115 Altera board.
. Two clk cycles, low latency, low hardware cost NoC . Virtual Channel (VC), wormhole based router . Non-speculative switch and VC allocation . Look-ahead routing . Fully parameterizable in terms of, VC number, buffer size and node-number . Platform independent . Wishbone adaptable NI . Mesh and Torus topology . parameterizable processing cores
The aeMB compiler can be downloaded from :
To Do List
. Support RTOS