Created: Jun 10, 2013
Updated: Jan 7, 2015
SVN Updated: May 14, 2014
Other project properties
System on Chip
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
PC AT SoC based on Next186 core. CPU runs at 33 MHz (up to 33 MIPS), 64MB of dynamic RAM, DOS6.22.
Able to run DOS 8086, 80186 applications (most of 80286 applications/games are running ok). May run real mode 32bit 386 applications with a 32bit software extender (see EMU386).
Implementation done and tested on Xilinx Spartan3AN evaluation board (with Xilinx ISE 14.5), occupying ~50% FPGA resources.
Video modes available: 80x25x256 text, 320x200x256 MCGA graphic, 640x480x256 VESA VBE mode 101h.
PS2 8042 controller for keyboard and mouse.
Simplified 8259 PIC, 8253 timer.
Bootstrap and BIOS ASM code provided.
Besides the FPGA board, a SD HC card is required for the hard disk implementation.
Theoretically, the system is able to run Windows3.0 in real mode if a VESA VBE 640x480x256 driver is provided (I was not able to find one available, or at least Windows3.0 DDK to write one).
All building blocks of this system are either developed by me, or are IP cores provided by Xilinx ISE.
CPU: Next186 core, (C) Nicolae Dumitrache, available on OpenCores.
VGA: A custom VGA core which implements the text mode 3h 80x25x256, the MCGA graphic mode 13h 320x200x256 and the VESA graphic mode 101h 640x480x256. The other CGA/EGA/VGA planar modes were of no interest for me, as the CPU and RAM are fast enough to support a decent linear 256 colors palette graphic mode. Unlike the standard VGA, the mode 13h can support 8 hardware pages.
TIMER: a simplified 8253
PIC: a simplified 8259 programmable interrupt controller
Kb, Mouse: a simplified 8042 PS2 controller
Hard Disk - a SD HC 4GB external memory card is used as HD. For simplicity, I access it in SPI mode, being able to get a transfer rate up to 2 MB/s. All the transfer work is done by the CPU, with a minimal hardware interface.
RS232: software driven interface, 1bit in and 1 bit out
NMI button (useful for debugging, see Turbo Debugger)
No DMA is necessary, as Next186 CPU is able to transfer up to 33MB/s with REP MOVSW.
More details are commented in the Verilog sources and in the BIOS code.
As for the IP cores, I used:
2KB FIFO (32bit in, 16bit out, independent clocks) for VGA
MIG DDRAM2 memory interface (slightly modified on some timings, as the original implementation was not working ok).
4KB true dual port 8bit SRAM for text mode font
2KB true dual port 8/32bit SRAM for 256bit VGA DAC color palette
2KB true dual port 32bit SRAM for CPU cache
one DCM for DDRAM and VGA
one DCM for CPU
The CPU clock is independent from DDRAM clock (133MHz), and it can be adjusted from the CPU DCM. I managed to make it work stable at 33.3333Mhz on Spartan3AN FPGA (up to 33MIPS). The bus interface between CPU and the cache memory is 32bit width and it is working at double the CPU frequency (66.6666MHz). All 8/16bit I/O CPU operations are done at 33.33333 MOP/s.
The system have no ROM, only 64MB of dynamic RAM and 4KB of code/data cache (8 lines of 256 bytes). In order to be able to boot, the cache is preloaded with the bootstrap code and marked as "dirty". At the first flush, the cache content will be transferred to RAM.
The bootstrap code tries to load the BIOS (8KB) from the latest 16 sectors of the SD card, at 0F000h:0E000h. If the SD card is not present, or BIOS is unavailable, the bootstrap code waits on RS232 (115200bps) an executable, loads it at 0f000h:100h and executes it.
The system uses all the dynamic RAM available on the Spartan3AN FPGA board (64MB at 133MHz). The memory is split as follows:
640KB low DOS memory
512KB video memory (which can be mapped over segments 0a000h and 0b000h)
224KB upper memory, available to DOS through the XMM manager
32KB ROM area, from which only the latest 8KB are actually used by the BIOS code.
2MB available for the old INT15h extended memory mechanism
The rest ~61MB is available as extended memory (XMM), and in my DOS configuration, is used as follows:
2MB for smartdrv (increases a lot the disk access)
28MB RAM disk (not really necessary, as the SD hard disk + smartdrv is fast enough, but 64MB RAM is too much for DOS)
16MB EMM (I use a LIMulator for 286)
The RAM is accessed in parallel by the CPU and the VGA. VGA uses a 2KB FIFO and have priority over CPU when the FIFO is empty.
When the FIFO is not empty, the CPU have priority.
The VGA bandwidth occupy max ~7% of DRAM transfer capacity (in 640*480 resolution), allowing the CPU to access the RAM
(including video RAM) with almost no penalty. The effective RAM (including video) CPU transfer rate is 20-30MB/s (and 40-60MB/s fill rate).
The RAM is divided in 64Kb pages. Each page can be mapped over each of the first 16 64Kb segment addresses. This mechanism is used for accessing the video memory in mode 13h (8 pages) and mode 101h VESA, and also for the extended/expanded memory access.
I provided in the package the assembler source code for the boot loader and for the BIOS.
The BIOS code is quite small, taking only 8KB beginning with 0f000h:0e000h. All the rest of the RAM upper memory is available for DOS.
The VESA VBE interface and all required paged memory access code for XMM is contained inside the BIOS.
A RS232 communication application executable is also provided (SerialComm.exe). It can be used to transfer applications or files from a PC to the Next186 SoC through a serial link.
Lately I installed GEOS (Geoworks Ensemble v2.0 and Breadbox Ensemble v4.1.2). With 16MB XMS swap space, almost 900KB global heap (in the first megabyte), and a CPU ~80 times faster than standard XT, it's working like a charm in VESA 640x480x256 colors.
Borland C++ v2.0, Turbo Pascal v7.0
Indy MCGA, Prince of Persia 2 MCGA
WordPerfect 6.0 VESA 640x480x256, BattleChess4000 VESA 640x480x256
GeoWorks Ensemble 2.0 VESA 640x480x256, Breadbox Ensemble v4.1.2 VESA 640x480x256
LATTICE MachXO2 -7000HE port
I uploaded the latest port of Next186 SoC, on the Valentin Angelovski's tiny but great FleaFPGA board (Lattice MachXO2-7000H, 32MB SDRAM,
It is working at 100Mhz SDRAM, 50Mhz bus, 25Mips) ~11000 Dhrystone 2.1
It takes ~78% FPGA area.
The SoC was extended with the following features:
- A20 address line, HMA area available
- added VGA mode 12h (640x480x16 - planar), allowing Windows3.0 to run (and also GEOS and Arachne web browser)
- added EGA mode 0dH (320x200x16 - planar), allowing a lot of old EGA DOS games to run
- ModeX support - more great DOS games are running (like Ultima Underworld, and Wolfenstein 3D - playable even in max screen mode).
- USB flash drive transfer