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Source code

Details

Name: i2c_wb_wrapper
Created: Nov 3, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: System on Chip
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License: LGPL

Description

Short: virtually convert an I2C slave into a WISHBONE slave
This is a wrapper for the I2C controller core by Richard Herveille ( http://opencores.org/project,i2c) which transparently converts a WISHBONE transaction into an I2C operation.
Example: a WB read/write of the WB address 09h of this core would schedule and execute the (long) list of commands needed to make an I2C read/write of reg 09h of an I2C device connected to the I2C controller core in OpenCores, and return the result transparently into the WB bus.
IMPORTANT: The current wrapper is for 16 bits I2C slaves, that is I2C reads and writes are composed of two bytes.

Features

- WISHBONE wrapper for the "I2C controller core" by Richard Herveille
- Fully transparent I2C WISHBONE operation
- A WB read/write of address X becomes an I2C read/write of reg. X and the I2C slave's response is sent back to the WB bus.
- Designed for 16 bits I2C slaves
- FPGA proven and works perfect (if you run into problems: take into account this I2C controller's bug solution: http://www.opencores.org/ptracker.cgi/view/i2c/370 )
- Limitations: the I2C slave's address is fixed, so that it may be used to control only one slave (can be overriden with minor modifications).

Status

- 03/11/2008: Project created on OpenCores