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Source code

Details

Name: robust_axi2apb
Created: Mar 28, 2011
Updated: Apr 19, 2011
SVN Updated: Jul 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error, APB response delay and slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools