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Source code


Name: robust_axi2ahb
Created: Apr 13, 2011
Updated: Jun 2, 2012
SVN Updated: Jul 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL


Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools