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Source code


Name: robust_axi_fabric
Created: Mar 23, 2011
Updated: Jun 12, 2015
SVN Updated: Jul 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools