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Source code


Name: robust_reg
Created: Mar 29, 2011
Updated: Mar 16, 2015
SVN Updated: Jul 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Mature
Additional info:
WishBone Compliant: No
License: LGPL


Generic APB register file generator. Creates Verilog source, C header file and HTML documentation, from an Excel worksheet. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools