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Source code


Name: robust_ahb_matrix
Created: Apr 13, 2011
Updated: Sep 21, 2013
SVN Updated: Jul 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL


Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according to input parameters: master number, slave number, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools