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Source code


Name: dma_axi
Created: Mar 25, 2011
Updated: Apr 29, 2011
SVN Updated: Apr 3, 2011

Other project properties

Category: System on Chip
Language: Verilog
Development status: Mature
Additional info:
WishBone Compliant: No
License: LGPL


Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control, timeouts and endianess swapping. Based on Provartec PR200 http://www.provartec.com/ipproducts