Go Back

Source code

Details

Name: dualspartainc6713cpci
Created: Jul 28, 2005
Updated: Apr 16, 2010
SVN Updated: Mar 10, 2009

Other project properties

Category: System controller
Language: Other
Development status: Stable
Additional info: Design done
WishBone Compliant: No
License:

Description

A project aimed at providing a DSP/FPGA based development board. Testing has begun, so far Power supplies, DSP, FPGAs have been proven to be 100% functional. Testing of the SDRAM and FLASH memories has be started and will require time for pattern read/write to be completed. If you are interested in this dev kit please contact me by my email address. I will be happy to call/email you back with more details. We have 3 more kits available, but will require assembling (typ. 2 weeks) before they can be shipped. We have not determined a price for kits yet, but reasonable offers will be accepted. We are also working a seconday IDE to the TI CCS to allow lower cost development. This is not a primary task as we have CCS2, but realise that for students/personal use CCS2 is too expensive. We are considering opening a compile farm to allow users to upload a project and receive a compiled a.out file that would be loaded into the Flash via HPI from a PC with download utilities. If you would like to help on this aspect, please contact me by email. A datashort is provided at http://www.qortek.com/products.aspx additionally you can contact QorTek for Pricing of Kits. Kit prices are determined to cover parts, pcb and assembly, or partial assembly. Sorry we can't give these away :( Nov 15, 2005 SDRAM was tested at full EMIF speed (100Mhz) Initial testing showed no problems. EMIF to WB_Master interface implemented. Tested working at 50Mhz, optimitize to work at 100Mhz. Nov 19 2005 DSP cards tested in cPCI chassis, and PCI bus testing began!! Working out a few issues between WB master and WB Slave on PCI core. Nov 23 2005 DSP and PCI core are talking via WB interface! WB bus speed has been droped to 50MHz due to PCI core timing constraints. A second cPCI communication card developed by QorTek is being programmed with the PCI core and an internal RAM Block for DSP to PCI access testing. A few schematic entry errors have been identified and fixed for a REV 1 release. None of the errors are show stoppers! A new release of the schematic will appear soon noting schemitcal errors. Dec 13th 2005 Lots of HDL coding and simulation and in system testing has been done. We are working to release a core for the board to connect the DSP to the PCI Core.

Features

- Standalone Operation w/ cPCI Interface
- PICMG 2.0 REV 3.0 ( pending testing )
- 3U cPCI Card or Standalone operation.
- Daughter Card interface for user defined hardware.
- 1 TI TMS320C6713GDP Processor 300MHz
- ALL GPIOs routed out to Daughter Card and FT256 BGA
- 1 Xilinx XC3S1000FG320 BGA ( Main bus interface/arbitrator )
- 1 Xilinx XC3SxxxxFT256 (User defined applications )
- All DSP GPIO available, user definable routing to External Interface
- DSP HPI Interface for programming / data exchange
- 4 40pin Header Daughter Card interface
- Fully qualified 32bit data/20bit Address bus
- 24 GPIO (SE) or 20 GPIO w/4DP (user definable) 8 Shared with Xinterface
- ALL DSP GPIO Pins available
- 1 68Pin (scsi like connector) External Interface/GPIO
- All Signal Routed to FT256
- 48 GPIO SE or 24 GPIO DP
- 1 External Reset thru FPGA
- 1 External Interrupt thru FPGA
- IO Vref, 3.3v, and Ground included.
- Multiple Power Supplies for FPGA VCCOs and DSP Core Voltage
- User adjustable. 4A Max (execpt FPGA Vaux)
- DSP Core voltages 1.2, 1.25, 1.4 (support all TI 6713 devices)
- External Interface/GPIO Voltage range 1.2-3.3v in 0.1v increments.
- FPGA Aux 2.5v (1.5A max)
- FPGA Internal 1.8v
- Includes Nexus (Altium Designer) JTAG Interface for interface to Nanoboard.
- Open to sugestions

Status

- Schematic Entry 100% done
- PCB Layout/Simulations 95% done
- PCB Testing/Assembly 50% done
- PCB Power up testing complete. All Power Supplies working.
- Power routing verified.
- PCB Assembly Started. (Third party assembly)
- Software / FPGA code 0% done
- WISHBONE compliant IP Core to Link DSP to PCI Core. 0% Done.
- WISHBONE compliant IP Core to Link Daughter Card IF to DSP/PCI Core.

Images

This board is 95% fully assembled.
http://opencores.com/project,dualspartainc6713cpci,DSP_near_done_tiny.jpg
We have begun writing FPGA and DSP code to link the PCI Bridge to the DSP and also allow users to program the DSP from the HPI.
More Imganes can be found here (not up to date, yet):
http://opencores.org/project,dualspartainc6713cpci,images

System Diagram

http://opencores.org/project,dualspartainc6713cpci,SystemDiagram.jpg