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Name: pci32tlite_oc
Created: Apr 29, 2005
Updated: Aug 24, 2009
SVN Updated: Apr 23, 2009

Other project properties

Category: System controller
Language: VHDL
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: Yes
License: LGPL

Description

The PCI32tLite IP core provides the funtionality of a PCI TARGET. The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC's in ALTERA CYCLONE II FPGA).
Whisbone databus size and endianess configurable: "BIG"/"LITTLE",32/16/8 bits.
PCI memory or I/O map configurable.
Uses BAR0 register; occupies 32Mbytes on PCI memory map or 512Bytes on PCI I/O map.

Status

Tested on HW:
- ALTERA MAXII Kit.
- XILINX Raggedstone1 board.
- Other custom HW.
PCI32TLITE_OC_HOWTO. Document to evaluate the PCI32TLITE IP Core creating "maxii_uart" project:
- Project to create a UART 16550 PCI peripheral using IP Cores from www.opencores.com:
- PCI32TLITE_OC(Peio Azkarate)
- A_VHDL_16550_UART(Howard LeFrevre)
- GH_VHDL_LIBRARY(George Huber and Howard LeFrevre)
- Permits easy evaluation of the IP on HW.
- Using PCI32TLITE_OC UART with LINUX serial standard driver.

Releases

R02 2007-09-19:
- "intb" and "serr" signals not defined as TRI. They have to be defined Opendrain in the FPGA (externally to the IP Core).
- Small changes due to onalib.vhd improvement.
- Removed TIMEOUT. Added wb_rty_i for Target termination with RETRY.
- Support Burst Cicles.
- Add Whisbone data bus configuration generics: WBSIZE and WBENDIAN
- Add wb_adr_o(1..0) signals.
- wb_dat_i,wb_dat_o,wb_sel_o size depends on WBSIZE.
- Advice: Change WB to/from PCI databus routing for "BIG"/16 WB configuration and DWORD PCI transactions (DWORD is not recomended when WB 16 configuration).

R03 2008-06-16:
- PCI32TLITE_OC_HOWTO Document added and maxii_uart project
- Add "1BARIO" configuration option for BARS generic.
- fix bug with WBENDIAN generic in pciwbsequ.
- Change PCI Burts to WB traslation behavior.
- Add "classcode" generic.
- Change BAR0 reset state to "0".
- Fix pcidmux bug for LITTLE/8 configuration.

R04 Next release.Not ready yet.
- Add "pci_" prefix to PCI Bus signals names.
- Change "rst" signal name to "pci_rst". And change from active High to active Low. Allowing straight-forward connection of the PCI32TLITE Core to PCI bus (without inverter on rst).
- Add PCI Can Controller project. Uses PCI32TLITE (Peio Azkarate) and CAN (Igor Mohor) IP Cores from Opencores.
- Add Linux driver for PCI Can Controller project.
- Add basic Linux driver for PCI32TLITE IP Core.
- Some suggestion or wishes contact me. Thanks.