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Source code

Details

Name: ata
Created: Sep 25, 2001
Updated: May 6, 2015
SVN Updated: Mar 10, 2009

Other project properties

Category: System controller
Language:
Development status: Stable
Additional info:
WishBone Compliant: Yes
License:

Description

ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface.
The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and CompactFlash and PC-CARD devices.

Status

- Three cores are available in VHDL and Verilog from OpenCores CVS via cvsweb or via cvsget.
- ToDo:
- Write documentation
- Start development of OCIDEC-4, featuring UltraDMA support

Development goals

The development of a range of software and function backward compatible cores with a growing set of features. Software can detect which version of the core is implemented by reading the Device-ID and Revision-Number from the status register, thus making it possible to use a single device driver to handle all cores. This gives designers/system integraters the ability to trade off complexity/resource usage to available feature set/performance. All cores are designed according to the latest ATA/ATAPI specs.

Currently three cores are available:

Device

OCIDEC-1

Features

Smallest core.
PIO transfer support only.
Single timing register for all accesses to the connected devices.

Intended use

Single PIO only devices (PC-CARDs, CompactFlash).
Designs requiring ATA capabilities, without the need for a complex feature set.

Gate usage

Altera ACEX EPF1k100FC484-1 262lcells@111MHz.


Device

OCIDEC-2

Features

Small core.
PIO transfer support only.
Common timing register for all compatible accesses to the connected devices.
Separate timing register per device for fast DataPort accesses.

Intended use

Dual PIO only devices (PC-CARDs, CompactFlash).
Designs requiring fast ATA capabilities, without DMA transfers.

Gate usage

Altera ACEX EPF1k100FC484-1: 439lcells@111MHz.


Device

OCIDEC-3

Features

PIO, Single-Word DMA and Multi-Word DMA transfer support.
Common timing register for all PIO compatible accesses to the connected devices.
Separate timing registers per device for fast PIO DataPort accesses.
Separate timing registers per device for DMA transfers.
PIO write access ping-pong.
WISHBONE Retry cycles for PIO accesses while controller busy.

Intended use

High speed ATA devices (Hard disks, CDROMs)
Designs requiring full featured ATA capabilities.

Gate usage

Altera ACEX EPF1k100FC484-1 916lcells@84MHz.

All cores feature a WISHBONE rev.B2 compliant interface, but can be adapted to any other kind of bus.
See the on-line documentation for more information. Note: This is a preliminary version. Not an official release.