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Source code


Name: ts7300_opencore
Created: Jun 12, 2006
Updated: Aug 16, 2008
SVN Updated: Mar 10, 2009

Other project properties

Category: Prototype board
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License: GPL


Boilerplate Verilog for use in Technologic Systems TS-7300 FPGA computer at http://www.embeddedARM.com/epc/ts7300-spec-h.htm Implements bus cycle demultiplexing to an internal 16 and 32 bit WISHBONE bus and 10/100 ethernet interface. Provided as a ready-to-compile Altera Quartus II project complete with pinlocks, compiler assignments, PLL setting, and timing constraints. A simple stub module implements a 32 bit register in the address space of the 200Mhz ARM9 CPU that toggles onboard LEDs as an easily extendable example of creating a WISHBONE slave. Once compiled, simply upload the ts7300_top.rbf bitstream file to the Linux filesystem on the SD card. The 200Mhz ARM9 processor runs Debian Linux out-of-the-box and includes a "load_ts7300" Linux command to configure the FPGA. No JTAG/ISP cables are required and FPGA configuration takes all of 0.2 seconds. The Quartus II tools required to compile the project are available free of charge (Quartus II 6.0 web-edition or later) from http://www.altera.com
Intended use of this project is both as a educational tool for evaluating and prototyping other open cores using the WISHBONE bus and as a jump start for Technologic Systems customers creating embedded products on the TS-7300 platform (or TS-7300 based custom designs). The inclusion of a 200Mhz GPP (general purpose processor) running Linux provides a powerful platform to study RC (reconfigurable computing) and combined hardware/software embedded design flows. The ethernet core included is the open source ethernet core project from http://opencores.org/project,ethmac,overview
Things on the TS-7300 the FPGA (Cylone2 2C8) is connected to:
- 8Mbyte SDRAM
- 16 bpp video DAC on DB15 VGA connector
- 10/100 Ethernet PHY #2
- 2nd SD card slot
- 8 RS232 serial ports
- 40 pin GPIO header (includes 2 LEDs)
- 224 megabytes address space to the 200Mhz EP9302 ARM9 CPU running Linux 2.4
The ARM9 CPU (Cirrus Logic EP9302) running Linux 2.4 is connected to:
- 32 to 128 MB SDRAM
- 32 to 128 MB NAND flash
- PC/104 expansion bus
- 1st SD card slot
- battery backed RTC
- 2 USB 2.0 high-speed host ports
- 10/100 Ethernet PHY #1
- 2 RS232/RS485 serial ports
- 6 user jumpers (JP1-JP6)
- 20 GPIO pins (for HD44780 LCD or matrix keypad)
- EP2C8 Cyclone2 FPGA
The default TS supplied bitstream includes support for all the above while the included project source only includes support for the ARM9 bus interface, GPIO, and ethernet. These other cores as well as a non-GPL'ed version of the included Verilog bus interface are available from Technologic Systems directly.

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DESCRIPTION: Technologic Systems TS-7300 FPGA Computer