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Name: sp6_pic32
Created: Apr 13, 2015
Updated: Apr 14, 2015
SVN Updated: Apr 13, 2015

Other project properties

Category: Prototype board
Language: VHDL
Development status: Mature
Additional info:
WishBone Compliant: No
License: LGPL

Description

Here i present a board with PCB and schematic included .
the board include :
-Spartan 6 FPGA (XC6SLX9)
-PIC32MZ2048 processor (High range processor from Microchip , 200Mhz MIPS core)
-high speed USB (device)
-Ethernet 100Mb/s with LAN8720 transceiver chip
-I/O header to FPGA pins : 18x 5.0V output (buffered with 74HCT04) and 20x 3.3V Input/output (no buffered)
the connection between CPU and FPGA include complete EBI (Enhanced bus interface) bus , which permit CPU to read/write FPGA registers (just like a coprocessor arrangment).
The board have been completely tested , in the case of a CNC motor controller.
As a note , the FPGA is rapidly full if trying to put a complex design in it with more than 100x 16bit regsiters , but it can support a medium design (with less than 100 registers ..)
The needed power supply is 5.0V , the board include switch converter chip(s) to produce 1.2V and 3.3V for FPGA core and I/O .
I have spare PCB or complete assembled boards for anyone interested.

board photo

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Spare pcb

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Bill of material

IC1 PIC32MZ2048ECH144 (QFP-144 - 0.5)
IC2 LAN8720 (QFN-24)
IC3 XC6SLX9 (QFP-144 - 0.5)
IC4,IC5 MP2105DJ (TSOT23-5 switch supply chip for FPGA and CPU)
IC6,IC7,IC8 74HCT04 (SOIC-1.27)
JP1 5V jack
USB usb type 'B'
RJ45 rj45 (Hanrun 911103A)
J1,J2,J3 JST-8P
JI1,JI2 JST-12P
JTAG JST-1.25-6P (JTAG connector)
ICSP JST-1.25-5P (ICSP connector)
L1 ferrite bead size 0805
L2,L3 inductor 4.7uH (Taido NR4018T4R7)
Led : standard RGB led (common anode)
OSC ASEMB-24Mhz (Abracon type ASEMB)

R1 10K 0603 (MCLR)
R2 1K 0603 (led)
R4,R5 330R 0603 (RJ45-leds)
R6 12.1K 0603 (phy)
R7 10R 0603 (phy2)
R9 10K 0603 (MDIO)
R10,R11 R10=2K2 R11=10K 0603 (supply 3.3V)
R12,R13 10K 0603 (supply 1.2V)
R14 330R 0603 (fpga done pin)
R15,R16 4K7 0603 (fpga program_b,init_b pins)
C1,C2 47uF 1206 (supply 1.2V)
C3 100nF 0603 (MCLR)
C5 47uF 1206 (CPU decoupling)
C6,C7,C8,C9 100nF 0603 ( MCU decoupling)
C10,C11 47uF 1206 (supply 3.3V)
C12,C13 4.7uF 0603 (phy)
C14,C15 100nF 0603 (phy)
C16 4.7uF 0603 (phy)
C17 1uF 0603 (phy)
C18 470pFb 0603 (phy)
C19 4u7 0603 (phy)
C20 100nF 0603 (phy)
C21 22nF 0603 (phy2)
C22 100nf 0603 (decoupling osc)
C23-C30 100nF 0603 (decoupling fpga)


pcb

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programming the FPGA

The FPGA can be configured by the JTAG connector and a Xilinx cable , but also by PIC32 CPU at startup (without needing additional flash memory or JTAG connection)
In ISE design suite , choose to generate a ".bin file" file , additionnaly to the ".bit file"
The bin data file can be sent directly by the CPU to the FPGA via DIN/CCLK pins .
This is very fast (0.5 s). the CPU drive the pins CCLK at 50Mhz without wait (maybe one or two NOP is enough wait )
the PIC32MZ2048 has 2048KByte flash, and can easily contain the FPGA configuration (300KB) as an uncompressed C array .
Note than other pins that can be driven / read by the CPU are:
INIT_B /DONE / PROGRAM_B . INIT_B and PROGRAM_B are used to reset the fpga and start programming . int is explained in Xilinx litterature.
DONE indicate successful operation , but it works all time , previsibly.

CPU to FPGA communication

The complete PIC32 EBI bus signals is connected in this card to the FPGA.
EBI is a 16 bit data / address bus that the PIC32 use to read/write to external peripherals .
the EBI speed is 100Mhz . So the data rate could be 100e^e6 x 16 bps.
the Spartan 6 FPGA does not need wait states,
For sync purpose , the FPGA registers could be doubled.
The EBI R/W and OE are connected to FPGA GCLK signals , this can ease timing design.
EBI include also CS (chip select ) for 4 peripherals , EBIRDY (for waits states in case of slow peripherals)
In this board , they is also additionally about 20 generic CPU I/O connected to generic FPGA pins.
The CPU RTS pins are able to output up to 100Mhz fixed clock if correctly configured (PIC32 COM BCLK mode ), this is used to clock the FPGA.

Schematic

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FPGA UCF

column 1 : FPGA pin
column 2 : CPU or HDR pin
column 3 : note

1 EBIA11
2 RB4
5 RB5
6 RE9
7 RE8
8 RA0
9 EBIA2
10 RG8
11 RG7
14 EBIOE GCLK
15 EBIWE GCLK
16 EBIA12 GCLK
17 EBIA6 GCLK
21 EBID7 GCLK
22 EBID6 GCLK
23 EBID5 GCLK
24 EBIA5 GCLK
26 EBID4
27 EBID3
29 EBID2
30 EBID1
32 EBID0
33 EBICS0
34 EBID8
35 EBID9
37 RG13 PROGRAM_B
39 RG14 INIT_B
40 EBID10
41 EBID11
43 EBID13
44 EBID12
45 EBID15
46 EBID14
47 IO1
48 IO2
50 IO3 GCLK
51 IO4 GCLK
55 IO5 GCLK
56 IO6 GCLK
57 IO7
58 IO8
59 IO9
61 IO10
62 NO1
64 NO2
65 RG12 DIN
66 NO3
67 NO4
70 RG15 CCLK
71 RA7 DONE
74 NO5
75 NO6
78 NO7
79 NO8
80 NO9
81 NO10
82 NO11
83 NO12
85 NO16 GCLK
87 NO17 GCLK
88 NO18 GCLK
92 NO13 GCLK
93 NO14 GCLK
94 NO15 GCLK
95 IO20 GCLK
97 IO19
98 IO18
99 IO17
100 IO11
101 IO12
102 IO13
104 IO14
105 IO15
111 IO16
112 EBIA4
114 EBIRDY1(86)
115 RB14
116 RB13
117 RB12
118 RF12
119 RF13
120 RA1
121 EBIA9
123 EBIA8 GCLK
124 EBIA3 GCLK
126 EBIA1 GCLK
127 RB11 GCLK
131 RB10(U4RTS) GCLK
132 EBIA7 GCLK
133 EBIA10 GCLK
134 RH3 GCLK
137 RA10
138 RA9
139 RB0
140 RB1
141 RB2
142 RB3
143 EBIA0

PCB file

in trunk folder of repository:
Altium designer project file : SP6_MZ
Gerber : SP6_MZ_gerber

pcb manufacturer that i recommend for quality of service : tingriver email:maisuid@gmail.com