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Details

Name: yellowstar
Created: Dec 12, 2001
Updated: Jul 8, 2013
SVN Updated: Mar 10, 2009

Other project properties

Category: Processor
Language:
Development status: Stable
Additional info:
WishBone Compliant: No
License:

IMAGE: ys_logo.jpg

FILE: ys_logo.jpg
DESCRIPTION: Yellow Star Logo

Description

It is capable of executing 32bit instructions based on the MIPS R3000 microprocessor instruction set and has been tested running large blocks of compiled C code.
Fully functional and compatible interrupt system. Can handle all exceptions cleanly and correctly.
Two 2Kbyte (Data and Instruction) direct mapped caches with coherency.
Memory management unit with 64 Entry TLB fully compatible to original design.
Designed in Powerview package but can be distributed in hierarchical schematic EDIF
Warning: The manual stated instructions SWL, SWR, LWL and LWR which are not implemented. And there are known bugs in the code.
For more information go to http://brej.org/yellow_star/
The processor was created using schematics and there is NO RTL VHDL or Verilog.

Features

- 32 entry 32bit Register bank created out of Ram blocks to save space
- 5 Stage pipeline
- Two 2Kb caches
- 64 Entry CAM TLB
- Exact exception handling
- One coprocessor

Status

- Tested running all instructions that are implemented.
- Tested and running correctly at 50MHz
- Memory menagement and caching buggy
- Looking for good schematic entry people to take control of the project
- Looking for people to convert the project files to other platforms