Created: Oct 12, 2014
Updated: May 31, 2015
SVN Updated: May 7, 2015
Other project properties
Development status: Beta
Additional info: FPGA proven
WishBone Compliant: Yes
This project is a soft processor core compatible with 586 instruction set.
It has been developped on Nexys4 board, with Artix7-100 FPGA with external SRAM and SPI flash.
The project contains the core and also a platform to demonstrate the core with interfaces for
external 16MB SRAM and 128Mbit SPI Flash.
The platform boots linux kernel with a ramdisk contained in the SPI flash.
The processor core has wishbone interface.
** CORE DETAILS:
- 586 instruction set implementation, conditional mov added.
- MMU with protected and paged mode supported with 4KB page size.
- TLB 8 entries
- CPUID (0x0617)and CMPXCHG8B are implemented, with conditional mov.
- pre-fetch queue is 32 bytes long.
- 8kB Instruction cache, 8kB Data cache, 128bit loaded at once into prefetch queue.
- Hardware multiplication and Division
- 32 bit wishbone interface with bursts.
- ~16000 dhrystones v2.1 @ 75MHz with -O2 option under gcc 4.6.2, no register, around ~ 9 VAX MIPS.
* Known limitations:
- no FPU, but emulation mechanism with "device not available" fault #7.
- some instruction are missing, but not used in Linux/GCC : like the decimal adjust.
- Protected and Paged mode are supported, there are some limitation in the protected
mode implementation like segment limit.
- bits and features for MSR/TSC/PAE/NX bit not implemented.
- MMU page size is 4KB , no PSE / PSE36 bit supported
- Segment prefix in protected mode are the default or GS descriptor, FS prefix
in protected mode is not used in Linux 32b.
- Minimal set of peripherals : timer and interrupt controller.
- one 16750 interface with 64byte fifo , re-used from uart16750 opencore project.
- IT87xx SuperIO chip implemented only for GPIOs parts. 16x GPIOs Connected to leds of nexys4.
( GPIO Linux driver fot IT87 compatible with userspace interface. )
- SPI interface serial-in , parallel out
- Bus Interface Unit to arbitrate between instruction fetch and data operations and
also MMU specific operation like updating the bit for page directory/table entries.
- The Platform mapping in the Artix7-100 fills 42% and clock frequency used in the project is 75MHz
- clock divider for timer and uart are hard coded for 75MHz base clock.
- internal ROM to boot and copy SPI flash into RAM, provide minimal description
and configuration for Linux with command line to configure TTY console on uart
at 115200 baud.
- SPI image with Linux 3.19 ( 3.17/3.14/3.12/2.6.x were tested as well) and initramfs
with busybox built from buildroot 2015.02 with dhrsytone/whetstone utilities.
- Kernel has been built on regular PC UBUNTU 14.04LTS with regular GCC as well.
- .config file for the kernel included, settings optimized for size and FPU emulation on.
- testbench and script to run under verilator simulator
- Structural Verilog with description in technology independent gates.
- Routing of such structure on FPGA is fast.
********** USEFUL NOTICE
notice: you need on nexys4 board to put SW1 and SW2 ON while SW0 is reset.
otherwise SW1-SW2 sets test modes.
toggle SW0 to reset/start the fpga.
More versions of the core are also available on
For instance evolutions with :
- different cache configurations and size
- optimization for lower area
- customizable/extendable instruction set for supporting custom vector opcodes.
- dual core versions
videos on youtube can be found here : https://www.youtube.com/channel/UCNbm8Bah54cwhedmCRWyXMA/videos
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