Created: Nov 20, 2005
Updated: Aug 4, 2010
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
UCore is a RISC microprocessor compatible of the MIPS32R2 Instruction Set. It can run all the MIPS32R2 instructions except the branch likely instructions. For these instructions are not recommended in the specification.
The processor has 6 pipeline stages: Instruction Fetch (IF), Instruction Decode (ID), Register Fetch (RF), Execution (EX), Memory Access (MEM) and Write Back (WB).
The processor uses synchronous ram as its Register file, data RAM and instruction RAM, which makes it be easily implemented in both FPGA and ASIC, especially in FPGA.
The processorÂ fs instruction set and privilege resource are designed strictly to the Â gMIPS32 Architecture for ProgrammersÂ h (Volume I-IIIÂ CRevision 2.50) specification from MIPS Technologies Inc.
The processor has been implemented in FPGA and synthesized by Design Compiler using UMC .18 ASIC libraries. When MMU and Caches are disabled, it can run at a speed 150MHz and occupies 3000 LUTs in Xilinx XC2VP30 (using Synplify 8.1 Pro and ISE 7.1i) FPGA; when implemented in Altera EP2C35 (using Quartus 6.0) FPGA, it can run at a speed of 120MHz and occupies 3300 LEs.
When using a MMU with 64 entries of fully associated TLBs, an 8KB data cache and an 8KB instruction cache, it occupies 13300 LUTs and can run at 46 MHz in XCV4LX160 FPGA.
According to the synthesis results of Design Compiler, the speed of the processor is 480 MHz and its power consumption is 197.6mW in Virtual SiliconÂ fs UMC .18 ASIC libraries, occupying 0.466 square millimeter silicon or 23,000 equivalents gates.
Many programs have been ported to the processor and tested on FPGA. They are uC/OS II, U-Boot, UIP/LWIP, Dhrystone, WEB&NAT server and so on. There are also some small test programs. The first one is an assembly program modified from the Plasma core written by Steve Rhoads, it tests all the instruction of UCore processor. The second and third ones are a 1000bits PI calculation program and a program sorting 10 short integers, which are written in C and compiled using GCC MIPS cross compiler.
Programs used to test the SDRAM, Flash, SRAM, VGA modules and a program used to download Motorola S-record format binary to the chip from UART are developed and tested, too. You can get detailed information from the Makefile locating in the tool dictionary.
I have built a system using the processor core. It contains the UCore, a 32k data/instruction on-chip SRAM, a timer, a UART, a SRAM controller, a SDRAM controller, a Nor Flash Controller, a VGA controller and a MAC controller and packet buffer for it. The system has been tested on AlteraÂ fs DE2 board and a Xilinx XC2VP30 FPGA board at 50MHz. All the programs mentioned in the previous section have been successfully run in FPGA.
I have run the Dhrystone benchmark version 2.1 in the system, and it's score is 141DMIPS when run at 100 MHz.
I have used GCC 3.2.3 and GCC 4.0.0 cross tool chains to generate the codes, then I translated them to format I need using a Perl script wrote by myself.
The scripts used to build the GNU tool chain is lying in test/utils dictionary, named build-gcc.sh. You can download the GNU tool chain source and use the script to build a cross tool chain of yourself.
I have verified the processor carefully. If anyone finds there are bugs in it, please let me know. IÂ fll fix it as quickly as possible. My email is firstname.lastname@example.org.
The code can be downloaded from the download section. The URL is http://www.opencores.org/pdownloads.cgi/list/ucore. ItÂ fs an old version of the system.
The latest version will be uploaded to CVS repository latter.
- Fully MIPS32R2 Compatilbe
- Verified on many FPGA board
- Confiugrable MMU and Cache modules