Created: Nov 26, 2007
Updated: Jun 13, 2012
SVN Updated: Jun 14, 2010
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
Only the SVN was updated.
I don't know how I can update the latest version download.
This is a stable Version of a 68000 compatible CPU.
It is an adapted Version to use with the Minimig Core.
"compatible" means that most of byte and word Instructions are cycle exact but many other Instructions are faster.
"adapted" means that the synchronous Mode, some bus control signals and the FC Out are missing. They are not needed for the minimig.
circa 3600 LC's on a ALTERA Cyclone II,
circa 2700 Slices an a XILINX Spartan 3,
Tested with the Dennis van Weeren Minimig Core on the C-One Board with FPGA Extender from Individual Computers.
Source Code and Bitstreamfiles here:
14.jun.2010 bugfix Movem with regmask=XFFFF and regmask=X0000
Add missing Illegal $4AFC
10.feb.2009 shift and rotation opcode
21.jan.2009 insert missing RTR opcode