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Source code

Details

Name: sub86
Created: Oct 25, 2012
Updated: Dec 18, 2012
SVN Updated: Jan 4, 2013

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL

Description

sub86 is a frugal 32bits cpu that executes a small subset of the legacy x86-32 instructions.
The core has been designed with a C compiler back end code generator with three focus :
- limit the number of opcode and instructions as much as possible.
- the resulting binary code must run functionally equivalent on real PC and on sub86 core.
- make the core as small as possible, by limiting the number of required hardware ressources ( alu , multiplier , number of registers : only EAX/EBX/ECX/EDX/ESP/EBP/PC/flags registers are implemented).
The status of the development (in Dec 2012) is debugging using dhrystone on a small subsystem, as of now the system shows
a 0.22DMIPS/MHz or 22DMIPS @ 100MHz.
Also test are on going for running a unix like os (xinu) in a 94kB snapshot.
The limited opcodes implemented creates bigger binaries, around 1.5x has been observed.
In the SVN repository there is only the verilog file for the core and no test bench, for the moment.