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Source code


Name: s1_core
Created: Jan 3, 2007
Updated: Oct 1, 2012
SVN Updated: Oct 2, 2012

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone Compliant: Yes
License: GPL

S1 Core briefly...

The S1 Core is a reduced version of the OpenSPARC T1 released by Sun Microsystems. While the T1 is a complete microprocessor with 8 cores (capable of running up to 32 concurrent threads) and includes a crossbar switch, L2 Caches and several other interfaces, the S1 takes only one 64-bit SPARC v9 core (capable of running from 1 up to 4 concurrent threads) and includes a Wishbone Master Interface to connect to the cores available on OpenCores.

For more details please refer to the Simply RISC website , or to the new OpenSPARC SoC project that contains several updates and bug-fixes.