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Source code


Name: rise
Created: Dec 6, 2006
Updated: Jan 26, 2007
SVN Updated: Feb 9, 2010

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info:
WishBone Compliant: No


RISE (Rarest Instruction Set Ever) is a pipelined 16-bit RISC processor with a simple instruction set. One outstanding feature of the instruction set is that all instructions are conditional, i.e. the execution of a instruction may depend on flags in the status register. The processor is equipped with 16 registers: 12 general purpose registers and 4 registers that have are reserved for specific functions (e.g. program counter). The HDL used for this project is VHDL. For further information on the instruction set architecture have a look at this page:


- 16-bit RISC CPU
- 16 registers
- Leightweight but powerful ISA
- Conditional instructions
- Pipelined: 5 stages


- Beginning of development phase