Created: Aug 1, 2014
Updated: Aug 29, 2014
SVN Updated: Aug 4, 2014
Other project properties
Development status: Beta
WishBone Compliant: No
This project is an implementation of a processor compatible with the instruction set of the RISCO architecture.
A description of the original RISCO ISA is available on http://hdl.handle.net/10183/21530.
An assembler and a compiler are available on https://code.google.com/p/risco-llvm/.