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Source code


Name: riscompatible
Created: Aug 1, 2014
Updated: Aug 29, 2014
SVN Updated: Aug 4, 2014

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info:
WishBone Compliant: No
License: LGPL


This project is an implementation of a processor compatible with the instruction set of the RISCO architecture.
A description of the original RISCO ISA is available on http://hdl.handle.net/10183/21530.
An assembler and a compiler are available on https://code.google.com/p/risco-llvm/.