Created: Dec 29, 2001
Updated: Jan 17, 2002
SVN Updated: Mar 10, 2009
Other project properties
Development status: Planning
WishBone Compliant: No
This project is my diploma paper i have written to gratuate at the University of Applied Sciences St.Gallen (Switzerland).
This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based.
Additionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port.
This core wasn't designed for commercial but for educational use. RAM, ROM and the ports are designed with the schematic editor from Xilinx ISE. RAM and ROM are dual ported for an additional access over a pci bridge. The CPU is programmed in VHDL.
The papers are written in german.