Created: Jan 17, 2002
Updated: Sep 9, 2011
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
A small RISC CPU (written in VHDL) that is compatible with the 12 bit opcode PIC family. Single cycle operation normally, two cycles when the program counter is modified. Clock speeds of over 40Mhz are possible when using the Xilinx Virtex optimizations.
Licensed under LGPL.
This core is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
You are responsible for any legal issues arising from the use of this core.
PIC is a trademark of Microchip Technology Inc.
The core has a single pipeline stage and is run from a single clock, so (ignoring program counter changes) a 40Mhz clock will give 40 MIPS processing speed. Any instruction which modifies the program counter, for example a branch or skip, will result in a pipeline stall and this will only cost one additional clock cycle.
The CPU architecture chosen is not particularly FPGA friendly, for example multiplexers are generally quite expensive. The maximum combinatorial path delay is also long, so to ease the place and route tool's job the core is written at a low level. It instantiates a number of library macros, for example a 4:1 mux. Two versions of these are given, one is generic VHDL and the second is optimised for Xilinx Virtex series (including Spartan devices). A constraints file locates the datapath macros within the device and ensures an easy fit and high clock speed.
Performance & Size
The core builds to around 110 Virtex CLBS (depending on synthesis).
>33 Mhz in a Virtex e - 6
>40 Mhz in a Virtex e - 8
Tested successfully on hw.
rel1.1 source zip released.
Added hex_conv software
Added rel1.1 source zip : bug fix
Used wrong bank select bits in direct addressing
INDF register returns 0 when indirectly read
FSR bit 8 always set
Added rel1.0 source zip :