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Source code


Name: potato
Created: Apr 8, 2015
Updated: Jun 18, 2015
SVN Updated: Jun 16, 2015

Other project properties

Category: Processor
Language: VHDL
Development status: Alpha
Additional info: Design done , FPGA proven
WishBone Compliant: Yes
License: BSD

The Potato Processor

The Potato Processor is an implementation of the 32-bit integer subset of the RISC-V ISA.

Notable features are:

  • Supports the full RV32I subset of the RISC-V ISA, version 2.0.
  • Supports the csrr\* and sret instructions from the RISC-V supervisor extensions draft, version 1.0.
  • Includes a simple, direct-mapped instruction cache for high-speed performance.
  • Includes a HTIF interface that can be used with the FROMHOST/TOHOST registers.
  • Includes a Wishbone interface for integration into Wishbone-based systems.

The processor has been tested on a Nexys 4 board from Digilent. The design used for testing is included in the source distribution, with instructions on how to get it up and running.

A rudimentary reference manual is available: Technical Reference Manual

Wishbone Details

The Wishbone interface for the processor, pp_potato has the following specifications:

Wishbone revision
Interface type
Address port width
32 bits
Data port width
32 bits
Data port granularity
8 bits
Maximum operand size
32 bits
Little endian
Sequence of data transfer

Planned Features

Additional features are planned for Potato. These features will be implemented in the future and it will be possible to turn most of them on or off using generic parameters when instantiating the processor. Planned features include (in prioritized order):

  • Support for the new supervisor spec, with new CSR names and instructions (in progress)
  • Data memory cache
  • Branch prediction
  • Hardware multiplication and division support (the M extension of the RISC-V ISA)
  • Compressed instructions support (the C extension of the RISC-V ISA)