Created: Oct 28, 2013
Updated: Apr 20, 2014
SVN Updated: Nov 1, 2013
Other project properties
Development status: Mature
Additional info: Design done , FPGA proven
WishBone Compliant: No
This project implements a single cycle core for the emulation of PIC16C5x microcomputers. The core requires the integrator to implement the I/O registers and program memory. The core provides these standard base architecture peripherals: timer, pre-scaler and clock multiplexer, and watchdog timer. The core provides selects and read/write strobes for the three I/O ports and the corresponding TRIS registers.
The timer peripheral supports all normal functions of the timer 0 in the PIC16C5x family of 12-bit instruction processors. A fully synchronous architecture for the clock source logic and the pre-scaler has been selected. This facilitates the integration of the core with FPGAs. The watchdog timer length is parameterized, so the period can be determined by the application and integrator.
PA is implemented, and the 2-deep stack is 12 bits in width. Thus, program memory can be extended to 4096 x 12 instead of the standard of 2048 x 12.
The core uses inference for all memory, and should be easily ported to any FPGA family that supports LUT or Block RAMs.
The core has been integrated into a Spartan 3A XC3S50A-4VQ100I FPGA using its the three block RAMs as a 4096 x 12 program memory. All instructions, except program branches, execute in a single memory cycle. Thus, as provided the core has been demonstrated in this application supporting a memory cycle rate greater than 60 MHz.
Tool Set Compatibility
This core has been used with MPLAB and the CCS C compiler tools. A utility for converting from Intel Hex to Xilinx MEM files has been provided as part of the M16C5x SoC project (found here on OpenCores).
When used in an implementation of a soft-core processor, the P16C5x exhibits the following results for synthesis in an XC3S50A-4VQ100I FPGA. As a module of the soft-core processor, the P16C5x core occupies 389 slices, utilizes 202 slice registers, and 488 LUTs.
The timing constraints used to achieve the best results with the -4 speed grade of the XC3S50A FPGA are shown in the following table:
|Met||Constraint||Check||Worst Case Slack||Best Case Achievable||Timing Errors||Timing Score|
|Yes||TS_Clk = PERIOD TIMEGRP "Clk" 16.666 ns HIGH 50%||SETUP/HOLD||0.011ns/0.651ns||16.655ns||0/0||0/0|
|Yes||TS_SPI_SCK = PERIOD TIMEGRP "SPI_SCK" 15 ns HIGH 50%||SETUP/HOLD||0.108ns/1.026ns||14.784ns||0/0||0/0|
|Yes||TS_Clk_UART = PERIOD TIMEGRP "Clk_UART" 10 ns HIGH 50%||SETUP/HOLD||0.513ns/0.680ns||9.487ns||0/0||0/0|
With the lower speed grade part, the P16C5x will operate at just over 60 MHz. The single cycle operation of this core provides a soft-core processor that delivers nearly 60 MIPs. ( Note: jumps, calls, and branches require two cycles, but all other instructions are single cycle instructions.)