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Source code


Name: nextz80
Created: Mar 18, 2011
Updated: Jul 3, 2014
SVN Updated: Feb 6, 2014

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
License: LGPL


- Z80 compatible processor.
- All documented / un-documented intstructions are implemented.
- All documented / un-documented flags are implemented.
- All (doc / un-doc) flags are changed accordingly by all (doc / un-doc)instructions. The block instructions (LDx, CPx, INx, OUTx) have only the documented effects on flags. The Bit n,(IX/IY+d) and BIT n,(HL) un-documented flags XF and YF are implemented like the BIT n,r XF and YF, not actually like on the real Z80 CPU.
- All interrupt modes implemented: NMI, IM0, IM1, IM2.
- R register available.
- Fast conditional jump/call/ret takes only 1 T state if not executed.
- Fast block instructions: LDxR - 3 T states/byte, INxR/OTxR - 2 T states/byte, CPxR - 4 T states / byte
- Each CPU machine cycle takes (mainly) one clock T state. This makes this processor over 4 times faster than a Z80 at the same clock frequency (some instructions are up to 10 times faster).
- Works at up to 40MHZ on Spartan XC3S700AN speed grade -4) - performances similar or better than a real Z80 running at 160Mhz.
- Small size (~12%, ~700 slices - on Spartan XC3S700AN).
- Tested with ZEXDOC (fully compliant) and with ZEXALL (all OK except CPx(R), LDx(R), BIT n, (IX/IY+d), BIT n, (HL) - fail because of the un-documented XF and YF flags).


The test bench is a micro computer based on NextZ80 processor (tested on Xilinx Spartan 3AN).
Main features:
- NextZ80 CPU running at 40 MHZ
- the CPU receives maskable interrupt at the end of each scan line. The interrupt vector is 0x00, allowing all IM modes (IM0 = NOP, IM1 = RST38, IM2 = jump at mem[I:0]). It can be used for border effects or for ink - paper - video memory effects.
- 32 KB static RAM
- VGA (640*480) screen, with 128 lines upper border, 80x24 characters (8x8 pixels each), and 160 lines lower border.
- screen buffer (1920 bytes) at address 0x7800
- character map (2048 bytes) at address 0x7000
- output port 1 - border color (R3G3B2)
- output port 2 - ink color (R3G3B2)
- output port 4 - paper color (R3G3B2)
- output port 8 - {bit0 = PS/2 clk, bit1 = PS/2 data, bit2 = RS232 TxD}
- input port 0 - scan line lower 8 bits
- input port 1 - { bit1:0 = scan line upper 2 bits, bit2 = PS/2 clk, bit3 = PS/2 data, bit4 = RS232 RxD}
- 1 DCM (supplied with 50 MHZ), providing the 25MHZ VGA clock and 120MHZ system clock.
- 1 reset button
- RS232 interface
- PS/2 keyboard interface
The CPU is fed with 120Mhz, but 2 from 3 states is in WAIT. This way, the CPU runs at 40Mhz, allowing one clock state for the video generator to read the memory (no contention between CPU and VGA).
The system clock is flexible, it can be adjusted from 120Mhz, by re-programming the DCM
The boot loader waits for RS232 (115200 bps) to receive a binary file. It places it at address 100h and then launches it. The binary file can be a .COM CP/M file, which uses at most BDOS 2 and 9 functions (print char and string) - this is the case for ZEXDOC.COM and ZEXALL.COM, which may be directly uploaded.
A RS232 communication application is provided (SerialComm).


Benchmark results:
The ZEXALL/ZEXDOC Z80 instruction exerciser takes 5min:16sec to finalize.
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