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Source code

Details

Name: ncore
Created: Oct 27, 2006
Updated: Oct 28, 2007
SVN Updated: Mar 10, 2009

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: GPL

Description

This is a little-little processor core. It has 16 instructions. It is under developement again, since the latest version is deleted... It is not yet verified, tested, etc.
It's written in Verilog, generaly for Spartan.

Features

-It's very little.
-Easy to understand.
-Easy to convert.
-Easy to compile the RISC or CISC instructions into this small set of commands.

Status

Ver 0.1
"post-alfa"
Ver 0.2
There was many errors of syntax...
So now there are corrected, it's ready to synthesize.
Not yet wholly tested.
New in downloads:
asm compiler C and Yacc/Lex versions (Alpha)
simple simulator to verify the compiled code
nCore 2: more procedure-capability
nCore 3: safe multi-tasking-capability

Under developement:
C, asm compilers, emulator, BIOS
Under planning:
OS with cooperativ/hybrid multitasking, handling the configuration of the multicore system.
Wishbone