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Source code


Name: mips_enhanced
Created: Nov 27, 2010
Updated: Apr 10, 2011
SVN Updated: Apr 9, 2011

Other project properties

Category: Processor
Language: Verilog & VHDL
Development status: Stable
Additional info:
WishBone Compliant: No
License: LGPL


This project is based on MIPS789 opencores project.We used MIPS789 core and added the cache infrastracture and AMBA bus from LEON3.The final core executes MIPS I instructions.It is downloaded on a Spartan3 fpga(gr-xc3s-1500).In order to test it we used the Leon3 Testbench.