Created: Mar 9, 2011
Updated: Nov 11, 2011
SVN Updated: Nov 9, 2011
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven
WishBone Compliant: No
This project is developed at Reconfigurable Computer Laboratory - FRM - UTN, and allows
simulate and synthetize the Simplez processor. It is a didactic processor created by
Gregorio Fernández in his book "Conceptos Básicos de Arquitectura y Sistemas Operativos",
This theoretical processor has a von Neuman architecture, with a set of eight instructions
and 512 memory words. Each twelve bits word, contains two fields: operation code and
data address. Basically, Simplez repeats cyclically the next three steps:
- Reads the instruction stored in a main memory's address.
- Decodes the instruction and executes it.
- Generates the address in the main memory of the next instruction.