Created: Jan 3, 2007
Updated: May 29, 2012
SVN Updated: Sep 7, 2009
Other project properties
Development status: Beta
Additional info: FPGA proven , Specification done
WishBone Compliant: Yes
M1 Core briefly...
The M1 Core is a 32-bit RISC CPU compatible with a popular GCC target.
It's been designed for simplicity and it's been used for some didactical activities at the University of catania.
The CPU is written in Verilog and it's been tested on FPGA (Xilinx Spartan-3E Starter Kit).
The CVS tree includes sources from other two OpenCores projects:
- wb_ddr developed by Joerg Bornschein
- ps2_interface developed by John Clayton