Created: Apr 8, 2005
Updated: Dec 20, 2009
SVN Updated: May 5, 2009
Other project properties
Development status: Stable
Additional info: Design done , FPGA proven , Specification done
WishBone Compliant: No
Extremely simple micro-controller allowing easy augmentation of the instruction set (e.g. a Hello World project for FPGA micros). Associated assembler written in C#. Example program displays a scrolling "Hello UJorld" on four digit/seven-segment display.
* A “Hello World” for FPGAs
e.g. a simple microprocessor core for use in a FPGA/VHDL course
* A Core that is easily extended with additional instructions, addressing modes,
* Exploits single port distributed RAM’s ability to do both sync write & async read.
* High performance, single pipeline stage micro-controller.
* Efficiently implement slow speed logic via emulation.
* Implement real-time software via compilation to EDIF.
One processor per interrupt and deterministic timing.
* 100+ Mhz, in a Spartan 3
* Uses 84 logic LUTs and one-half of a block RAM
* Single cycle instruction execution.
The design regimen is single pipeline stage micro-controller. Instruction fetch via block RAM read. Data fetch via distributed RAM asynchronous read. Data store via synchronous write coinciding with next instruction fetch (and register updates).
The instruction set includes no branches or calls. Program executes sequentially until HALT instruction. Then waits for next “system” clock.
Very simple assembler via subroutine calls (one subroutine for each unique instruction) which deposit binary into a list. List is formatted and written to text file suitable for pasting into block RAM initialization.
Lem1_9min_defs.vhd Instruction set
Lem1_9min_hw.vhd Test harness for Xilinx/Digilent Spartan-3 board
Form1.cs C# source for “assembler”
Lem1_9min_asm.csproj C# project for lem1_9min assembler, uses Windows form
No branch instructions. Program executes until reaching HALT instruction. Then waits for next "system" clock. Intended for logic emulation.
Single bit wide accumulator and memory. Carry bit available and with ADC (add with carry) instruction arithmetic is done bit serial.
Data memory kept in distributed RAM (Xilinx). Uses async read and sync write. In a single instruction clock cycle: program memory read, instruction address field addresses data memory and data memory read. Then instruction is performed followed by register updates. Register update also does distributed RAM write if enabled.
Fully functional and tested on Digilent Spartan-3 Starter board (www.digilentinc.com).
Considering several approaches to variable bit length instructions.
DESCRIPTION: PDF presentation
DESCRIPTION: micro-controller core
DESCRIPTION: Test harness
DESCRIPTION: Clock constraint and pin assignments
DESCRIPTION: C# assembler for lem1_9min
DESCRIPTION: C# project file for lem1_9min