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Name: jop
Created: Feb 19, 2004
Updated: Sep 5, 2011
SVN Updated: Mar 31, 2009

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: Yes
License: GPL


- VHDL files and and supporting tools for the design are available from OpenCores CVS.
- Actual updates are now in a git repository, see http://www.jopwiki.com/Download
- Further information can be found at http://www.jopdesign.com
- A wiki is available at http://www.jopwiki.com/


- Very small core:
- about 2000 LCs - 3000 LCs (configurable)
- fmax is 100 MHz in a Cyclone EP1C6
- Real-time features:
- architecture designed to simplify WCET analysis
- cycle accurate time interrupt (not tick based)
- real-time enhanced thread model
- WISHBONE master


JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design has been sucessfully implemented in low cost FPGA devices from Altera (ACEX 1K50, Cyclone) and Xilinx (Spartan II and Spartan-3).
JOP is open-source under the GNU General Public License, version 3.

Source checkout

The latest version of JOP can be obtained with anonymous GIT:
git clone git://www.soc.tuwien.ac.at/jop.git