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Source code


Name: i650
Created: Feb 18, 2015
Updated: Mar 26, 2015
SVN Updated: May 2, 2015

Other project properties

Category: Processor
Language: Verilog
Development status: Planning
Additional info:
WishBone Compliant: No
License: LGPL


A Verilog RTL implementation of the venerable IBM 650 computer.

The goal of this project is to use available source materials to recreate a 650 as accurately as possible.


Under active development. Control is currently being implemented and debugged in simulation.

About the IBM 650

Announced in 1953, the IBM 650 was a decimal, digit-serial vacuum tube computer. Main memory was a magnetic drum storing 2000 10-digit signed-decimal numbers. Machine logic was implemented using crystal diodes and vacuum tubes. It was arguably the most popular vacuum tube machine, with almost 2000 650's built and shipped.

IBM's practice at the time was to patent their computers in complete detail. US patent 2,959,351, "Data Storage and Processing Machine", filed Nov. 2, 1955, granted Nov. 8, 1960, includes complete schematics for the basic IBM 650 CPU, broken into many page-sized pieces. I have reassembled the original drawings and included them in this project.

During its lifetime, the 650 was upgraded with a number of features, including magnetic tape and RAMAC, one of the first hard drives.

Latches to Flip-Flops

This implementation is fully synchronous, using D flip-flops for sequential logic throughout. This has required reworking 650 sequential logic, beginning with basic timing. I have retained a four-phase clock, but with different semantics; all flip-flops are now triggered by the rising edge of one of the clock phases.

Phase A is considered a setup phase. Registers RAMs are read during phase A, making their early and on-time outputs available at posedge B, C and D. Timing pulses based on drum angular position are available at all phase posedges.

B, C and D phases are available for sequential logic based on values read from register or general storage. RAMs are written during phase D. In the original when multiple latches are cascaded, the cascaded result appears subject to the latch delays. In an equivalent synchronous sequential logic circuit, a full clock delay is imposed for each level of flip-flops. To afford maximum flexibility, the earliest possible posedge is chosen for each individual flip-flop. Paths through cascaded latches constitute the critical paths for the converted implementation; none may exceed 4 levels.

All early pulses, where “early" indicated a rising edge coincident with the D pulse, have been eliminated. The 650 used these to reset latches and then delay setting until the D pulse of the subsequent digit time, providing reset and ensuring that new inputs had time to settle before latching them.