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Name: hpc-16
Created: Sep 1, 2005
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info: Design done
WishBone Compliant: No
License: LGPL


- Isolate bus-controlling logic from Monolithic control-unit fsm
- adding support for other SoC buses (atleast AMBA)
- 2-pass assembler design (still pending).


Simple 16-bit microprocessor, 16-general purpose registers. custom instruction set, load-store RISC but current implementation "impl0" non piplined, control unit hardwired, 64K address space, total 16-interrupts (10 maskable), memory mapped i/o. Design wishbone (wb b.3) compatible bus cycles (currently single read/write), soon will add RMW. RTL (VHDL) completed & posted working for Verilog, prelim. documentation posted. Testing, fpga provening in progress and working for 2-pass assembler design (require your help!). The customized instruction set is mostly dervied from x86 subset. Also for procedure call and return follow x86 conventions, for interrupt handling use hybrid msc51 and x86 style. Due to these conventions pipelined impl would be difficult (any ideas...). Since many implementations are possible, these implementations will be organized as "impl", currently "impl0" specs and its vhdl implementation is completed, i'm also working for verilog version of "impl0".


- 16-bit Load-store RISC
- 64K addressable memory
- total 16 interrupts, 10 available to user


- RTL (VHDL) complete, also trying for verilog
- testing (almost!) complete
- not fpga proven