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Source code

Details

Name: hd63701
Created: Dec 20, 2013
Updated: Feb 15, 2014
SVN Updated: Feb 15, 2014

Other project properties

Category: Processor
Language: Verilog
Development status: Planning
Additional info: FPGA proven
WishBone Compliant: No
License: LGPL

Description

This project provides a synthesizable IP core compatible with HITACHI HD63701 processors.