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Source code


Name: edge
Created: Mar 1, 2014
Updated: Jun 29, 2014
SVN Updated: Mar 2, 2014

Other project properties

Category: Processor
Language: Verilog
Development status: Alpha
Additional info:
WishBone Compliant: No
License: LGPL


Edge is a microarchitecture implementation for mips1 ISA.
It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz frequency.
Supporting timer and other interrupt types and exceptions is implemented through co-processor0.
Edge has been tested and verified on Atlys that has a Spartan-6 XC6SLX45 FPGA.
For the Atlys board, UART driver is provided to communicate with PC at 115200 baud rate.
Youtube link for simple C programs running [1]