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Name: dfp
Created: Dec 15, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009

Other project properties

Category: Processor
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone Compliant: No
License:

Description

The data flow processor (DFP) is a flexible microprocessor written in VHDL which you can program down to the gate level to optimize your entire design. It is composed of 7 components with a specific data flow architecture. In most cases you just provide a VHDL file containing the program you want the processor to run, compile the whole design and then download it to an FPGA. For more specific designs, the code for the components can be altered to suit your needs. The components are:
TR - top register - top-most register for manipulating data or data flow
FU - function unit - provides functions to operate on data with TR and DS
DS - data stack - for holding intermediate data values
ME - memory - holds data, program and memory mapped I/O
PC - program counter - current address of program in memory
RS - return stack - holds values from PC for program nesting and return
IR - instruction register - runs instruction sequences from memory
By design, there is no bank of registers as in a conventional microprocessor design. This simplifies the instructions as they don't need a source or destination field. Instead, data items are pushed and popped to/from a stack. There is also no cache.
The idea is that since the FPGA ultimately will be manipulating data flows through it when it is running an application program, prebuilt soft processors ready for deployment and able to execute programs, can be used. While this is not new in of itself, the extension we add is flexibility, in that while the structure is there, it is also fully resizable and programmable. The depth of the stacks, the width of the data bus and the length of memory are all changeable parameters from 0,1,2... to chip limits.
The parameters are gleaned from compiling the code down to a hardware description language, VHDL in this case, for compiling or simulating with hardware tools.
In addition to changeable parameters, the instruction set is also programmable. When a DFP program is constructed, part of it will either define primitives, one or more instructions in a sequence, or include required ones from a library. The other part of a DFP program utilizes these primitives to form the basis language for the program. The program looks similar to assembler.
For more information, see the DFP and GCA websites:
http://members.shaw.ca/dataflowprocessor/
http://www.ece.ualberta.ca/strawbot/GCA/

IMAGE: dfp.gif

FILE: dfp.gif
DESCRIPTION: Structure of the DFP

Features

- VHDL coded Data Flow Processor
- VHDL coded RS232 interface, can be connected as a peripheral
- DFP Program compiler with full documentation and example programs
- DFP Program libraries including:
- basic assembler primitives
- stack manipulation primitives
- multi-step math implentations of addition, subtraction, multiplication, and division (see the DFP website for more info)
- Granular computing operations, including functionality for applications requiring fast fuzzy control

Status

- Fully synthesizable with Xilinx ISE 6.1 (make sure to turn off ROM extraction in the properties for Synthesize - XST, under HDL Options tab)
- Should be able to simulate with any VHDL simulator (tested with DirectVHDL, ModelSim, and Symphony EDA)
- 4/30/05 For the Windows platform, there is a newer compile of the Timbre tool used for creating VHDL code at:
http://members.shaw.ca/dataflowprocessor/Resources/DFP/DFPcompiler/
or
- major new release with many updates at:
http://members.shaw.ca/strawbot/GCA
- New website for natural artificial life forms using GCA technology:
http://members.shaw.ca/calf/