Created: Sep 3, 2003
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
Other project properties
Development status: Stable
WishBone Compliant: No
Cpugen (TM) generates customizable RISC cpu cores.
It allows direct customization of address/data/instruction bus size,
interrupt handling, indirect addressing, data/instruction latency
timings and custom instructions definition.
It is targeted to low size FPGAs, easy to use and getting started with.
GNU VHDL source code provided.
vendor dependent blocks (ex. memory blocks) are kept separate from vendor independent logic.
Customizable built-in assembler with data/instruction memory files generation; output file formats for the following environments:
In order to optimize logic resources and take advantage of FPGA flexibility; targeted to low size FPGAs; it permits to define:
- address/data/instruction bus size
- stack type/depth
- indirect address
- data/instruction variable latency
- custom instructions support
3) Graphical user interface:
4) Easy to use and getting started with: - Tutorial and example files are supplied with the package - Xilinx/Altera 4/8/16/32 bit cpu applications samples - GNU VHDL source code
- Current release 2.0
- VHDL simulations
- Tested on Altera and Xilinx evaluation boards
- Test/debug currently in progress
Please contact me for bugs reporting or for obtaining technical support.