Created: Mar 27, 2006
Updated: May 31, 2007
SVN Updated: Mar 10, 2009
Other project properties
Development status: Beta
Additional info: Design done
WishBone Compliant: No
- Initial tests and debugging have been performed.
- Initial code revision is 80-90% complete
- Initial cvs commit (27 Mar 2006)
Logical and arithmetic operations have been tested and are functional.
Pretty much everything works, as far as my test have shown. I've also writen some software that generates a ROM in VHDL from assembly source code. It's available at my website. Plus, there's an assembly simulator!
This is an implementation of an instruction set that I created. It's not a particularly useful thing to do, but it's something I've always been interested in. The instruction set bears a strong resemblance to the MIPS R3000, but this wasn't exactly deliberate. It's really the only instruction set I've been heavily exposed to. I'm keeping design documents and software I've written for this project on my website if anybody's interested. There's also a copy of the source and the modelsim project that I use, but it will most likely be updated less than the cvs version here.